A groundbreaking achievement has been marked in the realm of micro-computer technology with IBM’s innovative prototype chip. This compact chip, roughly the size of a fingernail, utilizes advanced 3D architecture to house about 100 billion transistors—almost double the transistor count of previously leading-edge chips.

IBM’s 10mm x 15mm chip is touted to be 70% more energy efficient and 50% more powerful than the current top-performing chips, with commercial applications expected within the next decade.

Traditionally, chip manufacturing process names have reflected the size of transistors in nanometers (e.g., 10nm or 5nm), with smaller sizes being advantageous for faster computations and lower energy consumption.

However, industry dynamics have evolved. According to IBM’s Fu Eimei, the nomenclature is now increasingly disconnected from actual physical dimensions and has become a marketing tool.

Although IBM refers to this new technology as “0.7 nanometers,” there is no assertion that individual transistors are that size. The true innovation—developed over 15 years—lies in the technique of stacking two silicon layers and creating electrical connections without overheating, all while ensuring mass manufacturability.

“Our industry has been scaling transistors along the X and Y axes for more than 60 years. This marks the first instance of enabling scaling in the Z direction,” Bu emphasizes.

While IBM has refrained from detailing the exact dimensions of this new technology, indications suggest it might involve two layers from its previously announced 2nm chip technology from 2021, which is already in production across renowned chip foundries worldwide. This advancement is expected to impact devices like the next Apple iPhone.

Given the immense complexity and expenses tied to chip design and production, the industry is collaborating on a technology roadmap led by a non-profit organization, aiming for coordinated advancements and market introductions by relevant stakeholders, including the Interuniversity Microelectronics Center. Although IBM’s 0.7nm technology remains untested in commercial environments, it is a crucial step forward in global chip manufacturing, likely prompting others to follow suit.

Bu foresees that the 0.7nm chips will find their way into consumer electronics within a decade, yet emphasizes that challenges related to quantum effects, current leakage, and additional issues arising at such diminutive scales will need to be addressed going forward. Some modern chips are now only 15 silicon atoms thick.

Owen Guy, a researcher from Swansea University, mentions that other chip manufacturers also claim similar high transistor densities, relying on multiple silicon layers separated by thick substrates. However, this method deviates from true 3D design, leading to complications in inter-layer connectivity and coolant distribution. “There’s considerable misunderstanding in the industry currently,” he notes.

The focus on downsizing transistors has reached a point where further reductions do not necessarily translate to smaller laptops or smartphones. The impetus to miniaturize components is primarily aimed at enhancing energy efficiency and cooling, extending battery life in mobile devices while decreasing power usage in data centers.

A significant hurdle now lies in integrating IBM’s new chip technology into global supply chains and consumer devices. Chips are produced in large quantities on 300mm silicon wafers, each containing trillions of transistors that are ultimately cut into individual components. These intricate machines conduct thousands of processes on the wafer, building layers of circuits, insulators, and various chemicals that are mere nanometers in thickness. Implementing unproven features, like IBM’s dual-layer system, poses considerable challenges.

Some manufacturers are striving to achieve even smaller 0.2nm technology, where circuit elements could be just one atom wide. “The ultimate boundary is one electron and one atom,” suggests Guy. “By around 2050, quantum technology may be essential for the next significant leap in chip innovation.”